Explicit Logical Effort Formulation for Minimum Active Area under Delay Constraints
نویسندگان
چکیده
This paper presents a gate sizing method which formulates minimum active area solutions under delay constraints. It is based on the logical effort delay model. Such minimization of transistor widths has direct impact on the power consumption and circuit area reduction. The explicit formulation of the method takes into account the maximum input capacitance, the output load to be driven, and the imposed timing constraint. Electrical simulations have shown maximum errors of 4.1% in power, 5.62% in delay, and 13.5% in transistor sizes. Keywords— active area minimization, gate sizing, logical effort, power minimization, design constraints.
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