Explicit Logical Effort Formulation for Minimum Active Area under Delay Constraints

نویسندگان

  • Caio G. P. Alegretti
  • Vinicius Dal Bem
  • Renato P. Ribas
  • André I. Reis
چکیده

This paper presents a gate sizing method which formulates minimum active area solutions under delay constraints. It is based on the logical effort delay model. Such minimization of transistor widths has direct impact on the power consumption and circuit area reduction. The explicit formulation of the method takes into account the maximum input capacitance, the output load to be driven, and the imposed timing constraint. Electrical simulations have shown maximum errors of 4.1% in power, 5.62% in delay, and 13.5% in transistor sizes. Keywords— active area minimization, gate sizing, logical effort, power minimization, design constraints.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

LEOPARD: A Logical Effort-based fanout OPtimizer for ARea and Delay1

We present LEOPARD, a fanout optimization algorithm based on the effort delay model for near-continuous size buffer libraries. Our algorithm minimizes area under required timing and input capacitance constraints by finding the tree topology and assigning different gains to each buffer to minimize the total buffer area. Experimental results show that the new algorithm achieves significant buffer...

متن کامل

A fanout optimization algorithm based on the effort delay model

This paper presents LEOPARD, a Logical Effort-based fanout OPtimizer for ARea and Delay, which relies on the availability of a (near) continuous size buffer library. Based on the concept of logical effort in VLSI circuits, the proposed algorithm attempts to minimize the total buffer area under the required time and input capacitance constraints by constructing the fanout tree topology and assig...

متن کامل

A Integer Non-linear Programming Model of Power Consumption of the Internet under QoS Constraints

The concept of energy-efficient networking has begun to spread in the past few years, gaining increasing popularity. According to several studies, the power consumption of the Internet accounts for around 10% of the worldwide energy consumption and is constantly increasing. On the other hand, with the increasing demand for various types of data traffic, especially delay sensitive traffic, the t...

متن کامل

Transistor Sizing for Low Power CMOS Circuits - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

AbstructA direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area. Analytical formulation for the pow...

متن کامل

Definition of P/N Width Ratio for CMOS Standard Cell Library

The efficiency of cell-based design synthesis of high performance circuit is strongly dependent on the content of the library. Great effort has been given in the design of libraries, to define the optimal selection of the logic gate drive strength. But few justifications are available to determine the P/N width ratio of each cell. In this paper we use an extension of the logical effort model to...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2013